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NCP1215A Low Cost Variable OFF Time Switched Mode Power Supply Controller
The NCP1215A is a controller for low power off-line flyback Switched Mode Power Supplies (SMPS) featuring low size, weight and cost constraints together with a good low standby power performance. The operating principle uses switching frequency reduction at light load by increasing the OFF Time. Also, when OFF Time expands, the peak current is gradually reduced down to approximately 1/4 of the maximum peak current to prevent from exciting the transformer mechanical resonances. The risk of acoustic noise is thus greatly diminished while keeping good standby power performance. A low power internal supply block also ensures very low current consumption at startup without hampering the standby power performance. A special primary current sensing technique minimizes the impact of SMPS switching on control IC operation. The choice of peak voltage across the current sense resistor allows dissipation to be further reduced. The negative current sensing technique offers advantages over a traditional approach by avoiding the voltage drop incurred by traditional MOSFET source sensing. Thus, the IC drive capability is greatly improved. Finally, the bulk input ripple ensures a natural frequency dithering which smooths the EMI signature.
Features http://onsemi.com MARKING DIAGRAM
8 8 1 SOIC-8 D SUFFIX CASE 751 1 6 TSOP-6 (SOT23-6, SC59-6) FACAYW G G SN SUFFIX CASE 318G 1 1215A ALYW G
6 1
* * * * * * * * * * * *
FAC = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
Variable OFF Time Control Method Very Low Current Consumption at Startup Natural Frequency Dithering for Improved EMI Signature Current Mode Control Operation Peak Current Compression Reduces Transformer Noise Programmable Current Sense Resistor Peak Voltage Undervoltage Lockout Pb-Free Packages are Available
PIN CONNECTIONS
SOIC-8 FB 1 8 7 6 5 (Top View) TSOP-6 CS GND CT 1 2 3 (Top View) 6 5 4 Gate VCC FB NC NC VCC Gate
CT 2 CS 3 GND 4
Typical Applications
Auxiliary Power Supply Standby Power Supply AC-DC Adapter Off-line Battery Charger
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2005
1
September, 2005 - Rev. 2
Publication Order Number: NCP1215A/D
NCP1215A
Line + + + FB CT CS N NC NC -
+
VCC GND Gate *
* If your application requires a gate-source resistor, please refer to design guidelines in this document.
Figure 1. Typical Application
FB
Feedback Loop Control
VDD Iref OFF Time Comparator Reference Regulator
- Voffset + CT 10 mA 0-7 V - +
+ -
VCC 12/8.5 V
Undervoltage Lockout
CS 12.5-50 mA
Set Q
Gate Driver Gate
Current Sense Comparator GND + - Reset Q
Figure 2. Representative Block Diagram
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NCP1215A
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PIN FUNCTION DESCRIPTION
TSOP-6 4 3 1 2 6 5 7 8 SO-8 1 2 3 4 5 6 7 8 Symbol FB Description The FB pin provides voltage feedback loop. The current injected into the pin determines the primary switch OFF time interval. It also influences the peak value of the primary current. Connection for an external timing programming capacitor. The CS pin senses the power switch current. Primary and internal ground. Output drive for an external power MOSFET. Power supply voltage and Undervoltage Lockout. Unconnected pin. Unconnected pin. CT CS GND Gate VCC NC NC
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MAXIMUM RATINGS
Rating Symbol VCC VFB Vin RqJA TJ Tstg VESD-HBM VESD-MM Value 18 Unit V V V C/W C C kV V Power Supply Voltage FB Pins Voltage Range -0.3 to 18 -0.3 to 10 178 150 -60 to +150 2.0 200 CS and CT Pin Voltage Range Thermal Resistance, Junction-to-Air (SOIC-8 Version) Junction Temperature Storage Temperature Range ESD Voltage Protection, Human Body Model (HBM) ESD Voltage Protection, Machine Model (MM) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device NCP1215ADR2 NCP1215ADR2G NCP1215ASNT1 NCP1215ASNT1G Package SOIC-8 SOIC-8 (Pb-Free) TSOP-6 TSOP-6 (Pb-Free) Shipping 2500 Units / Reel 2500 Units / Reel 3000 Units / Reel 3000 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCP1215A
ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TJ = 25C, for min/max values TJ = 0C to +105C, unless
otherwise noted.) Characteristic VOLTAGE FEEDBACK Offset Voltage Maximum CT Pin Voltage at FB Current = 25 mA (Including Voffset) Maximum CT Pin Voltage at FB Current = 50 mA (Including Voffset) CT PIN - OFF TIME CONTROL Source Current (CT Pin Grounded) Source Current Maximum Voltage Capability Minimum CT Pin Voltage (Pin Unloaded, Discharge Switch Turned On) CURRENT SENSE Minimum Source Current (IFB = 180 mA, CT Pin Grounded) Maximum Source Current (IFB = 0 mA, CT Pin Grounded) Comparator Threshold Voltage Propagation Delay (CS Falling Edge to Gate Output) GATE DRIVE Sink Resistance (Isink = 30 mA) Source Resistance (Isource = 30 mA) POWER SUPPLY VCC Startup Voltage Undervoltage Lockout Threshold Voltage Hysteresis (Vstartup - VUVLO) VCC Startup Current Consumption (VCC = 8.0 V) VCC Steady State Current Consumption (CGATE = 1.0 nF, fSW = 100 kHz, FB open) Vstartup VUVLO Vhys ICC-start ICC-SW - 7.2 2.2 - 0.55 12.5 9.0 3.5 2.8 0.9 14.2 - - 6.5 1.75 V V V mA mA ROL ROH 25 55 40 80 90 130 W W ICS-min ICS-max Vth tdelay 8.0 40 15 - 12.5 49 42 215 16 58 80 310 mA mA mV ns ICT VCT-max VCT-min 8.0 - - 9.8 6.5 - 11.5 - 20 mA V mV Voffset VCT-25mA VCT-50mA 1.05 2.4 3.6 1.19 3.1 4.6 1.34 4.3 6.2 V V V Symbol Min Typ Max Unit
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NCP1215A
TYPICAL CHARACTERISTICS
11.6 11.5 11.4 VUVLO, (V) 0 25 50 75 100 125 11.3 11.2 11.1 11.0 -25 8.8 8.7 8.6 8.5 8.4 8.3 8.2 -25
Vstartup, (V)
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 3. Vstartup Threshold vs. Junction Temperature
0.990 0.985 ICC-SW, (mA) 0.980 0.975 0.970 0.965 0.960 -25 Voffset, (V) 1.20 1.18 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 0 25 50 75 100 125 1.00 -25
Figure 4. VUVLO Threshold vs. Junction Temperature
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 5. Operating Current Consumption vs. Junction Temperature
Figure 6. Offset Voltage vs. Junction Temperature
49.0 48.5 48.0 ICS-max, (mA) 47.5 47.0 46.5 46.0 45.5 -25 0 25 50 75 100 125 VCS-th, (mV)
65 60 55 50 45 40 35 30 -25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 7. Current Sense Source Current vs. Junction Temperature http://onsemi.com
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Figure 8. Current Sense Threshold vs. Junction Temperature
NCP1215A
10.0 9.9 VCT-min, (mV) 0 25 50 75 100 125 9.8 ICT, (mA) 9.7 9.6 9.5 9.4 -25 16
14
12
10
8
6 -25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 9. CT Pin Source Current vs. Junction Temperature
120 100 Rsource-Rsink, (W) 80 60 40 20 0 -25 ICS, (mA) 60.0
Figure 10. CT Pin Threshold vs. Junction Temperature
TJ = 25C Rsource 50.0 40.0 30.0 20.0 10.0 0.0
Rsink
0
25
50
75
100
125
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
Ifb, FEEDBACK CURRENT (mA)
Figure 11. Drive Sink and Source Resistance vs. Junction Temperature
Figure 12. Current Sense Source Current vs. Feedback Current
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NCP1215A
APPLICATION INFORMATION The NCP1215A implements a current mode SMPS with a variable OFF time dependant upon output power demand. It can be seen from the typical application that NCP1215A is designed to operate with a minimum number of external component. The NCP1215A incorporates the following features: * Frequency Foldback: Since the switch-off time increases when power demand decreases, the switching frequency naturally diminishes in light load conditions. This helps to minimize switching losses and offers excellent standby power performance. * Very Low Startup Current: The patented internal supply block is specially designed to offer a very low current consumption during startup. It allows the use of a very high value external startup resistor, greatly reducing dissipation, improving efficiency and minimizing standby power consumption. * Natural Frequency Dithering: The quasi-fixed ton mode of operation improves the EMI signature since the switching frequency varies with the natural bulk ripple voltage. * Peak Current Compression: As the load becomes lighter, the frequency decreases and can enter the audible range. To avoid exciting transformer mechanical resonances, hence generating acoustic noise, the NCP1215A includes a patented technique, which reduces the peak current as power goes down. As such, inexpensive transformer can be used without having noise problems. * Negative Primary Current Sensing: By sensing the total current, this technique does not modify the MOSFET driving voltage (Vgs) while switching. Furthermore, the programming resistor together with the pin capacitance, forms a residual noise filter which blanks spurious spikes. Also fixing primary current level to a maximum value sets the maximum power limit. * Programmable Primary Current Sense: It offers a second peak current adjustment variable which improves the design flexibility. * Secondary or Primary Regulation: The feedback loop arrangement allows simple secondary or primary side regulation without significant additional external components. A detailed description of each internal block within the IC is given in the following text.
Feedback Loop Control
The main task of the Feedback Loop Block is to control the SMPS output voltage through the change of primary switch OFF time interval. It sets the peak voltage of the timing capacitor, which varies upon the output power demand. Figure 13 shows the simplified internal schematic:
VCC Current Mirror 1:1 17 k FB Current Mirror 1:1 Voffset + To OFF Time Comparator -
45 k
Figure 13. Feedback Loop - OFF Time Control
The voltage feedback signal is sensed as a current injected through the FB pin.
OFF Time Comparator Input Voltage
VDD
Voffset
0 mA
FB Pin Sink Current
Figure 14. FB Loop Transfer Characteristic
The transfer characteristic (output voltage to input current) of the feedback loop control block can be seen in Figure 14. VDD refers to the internal stabilized supply whereas the offset value sets the maximum switching frequency in lack of optocoupler current (e.g. an output short-circuit). To keep the switching frequency above the audio range in light load condition the FB pin also regulates in certain range the peak primary current. The corresponding block diagram can be seen from Figure 15.
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NCP1215A
To Current Sense Comparator 17 k FB Current Mirror 4:3 37.5 mA 12.5 mA CS Voffset + Voffset to VDD CT - + To Latch's Set Input - From Feedback Loop Block
Figure 15. Feedback Loop - Current Sense Control
The resulting current sense regulation characteristic can be seen from Figure 16.
50 mA CS Pin Source Current
10 mA CT
To Latch's Output
GND
Figure 17. OFF Time Control
12.5 mA
During the switch-ON time, the CT capacitor is kept discharged by a MOSFET switch. As soon as the latch output changes to a low state, the voltage across CT created by the internal current source, starts to ramp-up until its value reaches the threshold given by the feedback loop demand.
50 mA FB Pin Sink Current 100 mA 140 mA V
0 mA
Figure 16. Current Sense Regulation Characteristic
VDD Pout Goes Down CT Pin Voltage Pout Goes Up P3 Voffset P1 toff-min t P2
When the load goes light, the compression circuitry decreases the peak current. This has the effect of slightly increasing the switching frequency but the compression ratio is selected to not hamper the standby power.
OFF Time Control
The loop signal together with the internal current source, via an external capacitor, controls the switch-off time. This is portrayed in Figure 17.
Figure 18. CT Pin Voltage (Pout1 u Pout2 u Pout3)
The voltage that can be observed on CT pin is shown in Figure 18. The bold waveform shows the maximum output power when the OFF time is at its minimum. The IC allows an OFF time of several seconds.
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NCP1215A
Primary Current Sensing
The primary current sensing circuit is shown in Figure 19.
FB Feedback Loop Control
CS
12.5 mA B 50 mA + - To Latch
The primary current sensing method we described, brings the following benefits compared to the traditional approach: * Maximum peak voltage across the current sense resistor is determined and can be optimized by the value of the shift resistor. * CS pin is not exposed to negative voltage, which could induce a parasitic substrate current within the IC and distort the surrounding internal circuitry. * The gate drive capability is improved because the current sense resistor is located out of the gate driver loop and does not deteriorate the turn-on and also turn-off gate drive amplitude.
Gate Driver
Vshift
Rshift RCS VCS
GND
Iprimary
Figure 19. Primary Current Sensing
When the primary switch is ON, the transformer current flows through the sense resistor Rcs. The current creates a voltage, Vcs which is negative with respect to GND. Since the comparator connected to CS pin requires a positive voltage, the voltage Vshift is developed across the resistor Rshift by a current source which level-shifts the negative voltage Vcs. The level-shift current is in range from 12.5 to 50 mA depending on the Feedback Loop Control block signal (see more details in the Feedback Loop Control section). The peak primary current is thus equal to:
Ipk + Rshift *I RCS CS
(eq. 1)
The Gate Driver consists of a CMOS buffer designed to directly drive a power MOSFET. It features an unbalanced source and sink capabilities to optimize turn ON and OFF performance without additional external components. Since the power MOSFET turns off at high drain current, to minimize its turn-off losses the sink capability of the gate driver is increased for a faster turn-off. To the opposite, the source capability is lower to slow-down power MOSFET at turn-on in order to reduce the EMI noise. Whenever the IC supply voltage is lower than the undervoltage threshold, the Gate Driver is low, pulling down the gate to ground. It eliminates the need for an external resistor.
Startup Circuit
An external startup resistor is connected between high voltage potential of the input bulk capacitor and VCC supply capacitor. The value of the resistor can be calculated as follows:
Rstartup + Vbulk * Vstartup Istartup
(eq. 2)
A typical CS pin voltage waveform is shown in Figure 20.
V Ishift = 50 mA
VCC voltage at which IC starts operation (see spec.) Istartup Startup current Vbulk Input bulk capacitor's voltage Since the Vbulk voltage has obviously much higher value than Vstartup the equation can be simplified in the following way:
V Rstartup + bulk Istartup
(eq. 3)
Where: Vstartup
Ishift = 12.5 mA
The startup current can be calculated as follows:
0 Switch Turn-on t
Istartup + CVcc
Vstartup ) ICC-start tstartup
(eq. 4)
Figure 20. CS Pin Voltage
Figure 20 also shows the effect of the inductor current of differing output power demand.
Where: CVcc tstartup ICC-start
VCC capacitor value Startup time IC current consumption (see spec.)
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NCP1215A
If the IC current consumption is assumed constant during the startup phase, one can obtain resulting equation for startup resistor calculation:
Rstartup + CVcc
Vstartup tstartup
Application Design Example
Vbulk ) ICC-start
(eq. 5)
An example of the typical wall adapter application is described hereafter. As a wall adapter it should be able to operate properly with wide range of the input voltage from 90 VAC up to 265 VAC. The bulk capacitor voltage then can be calculated:
Vbulk- min + VAC- min 2 + 90 * 2 + 127 VDC
(eq. 11)
Switching Frequency
The switching frequency varies with the output load and input voltage. The highest frequency appears at highest input voltage and maximum output power. Since the peak primary current is fixed, the on time portion of the switching period can be calculated:
ton + Lp Ipk Vbulk
(eq. 6)
Vbulk- max + VAC- max 2 + 265 * 2 + 375 VDC
(eq. 12)
The requested output power is 5.2 Watts. Assuming 80% efficiency the input power is equal to:
P Pin + out + 5.2 + 6.5 W h 0.8
(eq. 13)
Where: Lp Transformer primary inductance Ipk Peak primary current Using equation for peak primary current estimation the switch-on time is:
ton + Lp Rshift 50 * 10-6 Rcs * Vbulk
(eq. 7)
The average value of input current at minimum input voltage is:
Iin-avg + Pin + 6.5 + 51.2 mA (eq. 14) 127 Vbulk- min
The suitable reflected primary winding voltage for 600 V rated MOSFET switch is:
Vflbk + 600 V * Vbulk- max * Vspike (eq. 15) + 600 * 375 * 100 + 125 V
Minimum switch-on time occurs at maximum input voltage:
ton- min + Lp Rshift 50 * 10-6 (eq. 8) Rcs * Vbulk- max
Using calculated flyback voltage the maximum duty cycle can be calculated:
d max + Vflbk Vflbk ) Vbulk- min 125 + + 0.496 + 0.5 125 ) 127 2 * Iin-avg d max -3 + 2 * 51.2 * 10 0.5
(eq. 16)
As it can be seen from the above equation, the switch-on time linearly depends on the input bulk capacitor voltage. Since this voltage has ripple due to AC input voltage and input rectifier, it allows natural frequency dithering to improve EMI signature of the SMPS. The switch-off time is determined by the charge of an external capacitor connected to the CT pin. The minimum toff value can be computed by:
V toff- min + CT offset + CT 1.2 ICT 10-5 + 0.12 * 106 CT
(eq. 9)
Following equation determines peak primary current:
Ippk +
(eq. 17)
+ 204.7 mA
Where: Voffset Offset voltage (see spec.) ICT CT pin source current (see spec.) The maximum switching frequency then can be evaluated by:
fsw- max + 1 ton- min ) toff- min (eq. 10) 1 + Lp * Rshift -6 ) 0.12 * 106 * CT * 50 * 10
Vbulk * Rcs
The desired maximum switching frequency at minimum input voltage is 75 kHz. The highest switching frequency occurs at the highest input voltage and its value can be estimated as follows:
f max -high + f max -low Vbulk- max d Vbulk- min max(eq. 18)
+ 75 * 103 375 0.5 + 110.7 kHz 127
This frequency is much below 150 kHz, so that the desired operating frequency can be exploited for further calculation of the primary inductance:
V * d max Lp + bulk- min Ippk * fsw- max 127 * 0.5 + + 4.14 mH 0.2047 * 75 * 103
(eq. 19)
As output power diminishes, the switching frequency decreases because the switch-off time prolongs upon feedback loop. The range of the frequency change is sufficient to keep output voltage regulation in any light load condition.
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NCP1215A
The EF16 core for transformer was selected. It has cross-section area Ae = 20.1 mm2. The N67 magnetic allows to use maximum operating flux density Bmax = 0.28 Tesla. The number of turns of the primary winding is:
np + Lp * Ippk B max * Ae
The voltage drop across the sense resistor needs to be recalculated:
VCS + RCS * Ippk + 2.7 * 0.2047 + 0.553 V (eq. 25)
Using the above results the value of the shift resistor is:
V Rshift + CS + 0.553 + 11.06 kW + 11 kW ICS 50 * 10-6 (eq. 26)
(eq. 20)
-3 + 4.14 * 10 * 0.2047 + 150 turns 0.28 * 20.1 * 10-6
The AL factor of the transformer's core can be calculated:
AL + Lp (np)2 -3 + 4.14 * 10 * + 184 nH (150)2
(eq. 21)
The value of timing capacitor for the off time control has to be calculated for minimum bulk capacitor voltage since at these conditions the converter should be able to deliver specified maximum output power. The value of the timing capacitor is then given by the following equation:
CT + +
1 fsw
For an adapter output voltage of 6.5 V, the number of turns of the secondary winding can be calculated accounting Schottky diode for output rectifier as follows:
(Vs ) Vfwd)(1 * d max)np ns + d max * Vbulk- min +
*V
Lp * Ippk bulk- min
1.2 * 106
1 75 * 103 *3
(eq. 27)
* 4.14 * 10127 * 0.2047 + 55.5 pF + 56 pF 0.12 * 106
(eq. 22)
(6.5 ) 0.7)(1 * 0.5)150 + 8.5 + 9 turns 0.5 * 127
The value of the startup resistor for startup time of 200 ms and VCC capacitor of 200 nF is following:
Rstartup + + Vbulk- min CVcc tstartup ) ICC-start MAX
Vstartup
The number of turns for auxiliary winding can be calculated similarly:
(Vs ) Vfwd)(1 * d max)np ns + d max * Vbulk- min
200 * 10-9
127 12 ) 10 * 10-6 0.2
(eq. 28)
(eq. 23)
(12 ) 1)(1 * 0.5)150 + + 15.35 + 15 turns 0.5 * 127
+ 5.77 MW + 5.6 MW
The peak primary current is known from initial calculations. The current sense method allows choosing the voltage drop across the current sense resistor. Let's use a value of 0.5 V. The value of the current sense resistor can then be evaluated as follows:
V RCS + CS + 0.5 + 2.442 W + 2.7 W 0.2047 Ippk
(eq. 24)
The result of all the calculations is the application schematic depicted in Figure 21.
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J1 1 Line C8 3 D1 L1 T1 2.2 mH J2 1 Neutral C1 4 2.2 mF/ 400 V + C2 2.2 mF/ 400 V + R3 C5 2M7 D5 100 nF R4 LL4448 IC1 C3 10 nF C4 56 pF 3 11 k R2 R1 2.7 4 CS GND NCP1215A ISO1 2 CT NC2 7 X VCC Gate 6 5 1 FB 2M7 NC1 8 X R5 220 C6 100 nF R6 47 k R7 47 k 1 nF/ 500 V C7 4 8 D9 MBRS360T3 C9 3 1 + C10 10 mF/ 16 V 5 470 mF/ 16 V + L2 4.7 mH R8 220 J3 1 +6.5 V@ 800 mA 1 nF/Y
2 - S250 + 1
R9 1k 2
D8
MURA160T3 Q1 MTD1N60
D7 BZX84C5V6
J4 1 GND
PC817
Figure 21. Adaptor Application Schematic
The following oscilloscope snapshots illustrate the operation of the working adapter. The Channel 3 in Figure 22 shows CT pin voltage at full output load. The Channel 1 is a gate driver output.
The CT voltage at no load condition is depicted in Figure 23.
Figure 22. CT Voltage at Full Load Condition
Figure 23. CT Voltage at No Load Condition
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Figure 24 shows CT voltage and also by Channel 2 the switch's drain voltage at light load conditions. Figure 26 demonstrates the reduction of the peak primary current at light load conditions.
Figure 24. CT and Drain at Light Load
Figure 26. CS Pin at Light Load Condition
The waveform on the current sense pin at full load conditions can be observed from Channel 3 in Figure 25.
Gate-Source Resistor Design Guidelines
In some applications, there is a need to wire a resistor between the MOSFET gate and source connections. This can preclude an eventual MOSFET destruction if, in the production stage, the converter is powered whilst the gate is left unconnected. However, dealing with an extremely low startup current implies a careful selection of the gate-source resistance. With the NCP1215A, the gate-source resistor must be calculated to allow the growth of the VCC capacitor to 4.0 V in order to not interfere with the power-on sequence. The following equation helps deriving Rgate-source, accounting for the minimum rectified input voltage and the startup resistor: Vinmin x Rgate-source/(Rgate-source + Rstartup) u 4.0 V. If we take a Vinmin of 100 VDC, a startup resistor of 4.0 MW, then Rgate-source equals 180 kW as a minimum normalized value.
Figure 25. CS Pin at Full Load Condition
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NCP1215A
PACKAGE DIMENSIONS
SOIC-8 D SUFFIX CASE 751-07 ISSUE AG
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP1215A
PACKAGE DIMENSIONS
TSOP-6 CASE 318G-02 ISSUE P
D
6
5 1 2
4 3
HE
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 1.50 1.70 0.95 1.05 0.40 0.60 2.75 3.00 10 - INCHES NOM 0.039 0.002 0.014 0.007 0.118 0.059 0.037 0.016 0.108 -
b e q 0.05 (0.002) A1 A L c
DIM A A1 b c D E e L HE q MIN 0.90 0.01 0.25 0.10 2.90 1.30 0.85 0.20 2.50 0
MIN 0.035 0.001 0.010 0.004 0.114 0.051 0.034 0.008 0.099 0
MAX 0.043 0.004 0.020 0.010 0.122 0.067 0.041 0.024 0.118 10
SOLDERING FOOTPRINT*
2.4 0.094
1.9 0.075
0.95 0.037 0.95 0.037
0.7 0.028 1.0 0.039
SCALE 10:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP1215A
The product described herein (NCP1215A), may be covered by the following U.S. patents: 6,385,060, 6,605,978. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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NCP1215A/D

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